Debian Electronics Digital design packages

Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.

Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.

The authors of arachne-pnr have now prepared its successor 'nextpnr'.

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Drawtiming is a command-line tool for documenting hardware designs through timing diagrams. In inputs textual signal descriptions and outputs image timing diagrams in many possible formats.

GHDL is a compiler and simulator for VHDL, a Hardware Description Language. GHDL is not an interpreter: it allows you to analyse and elaborate sources to generate machine code from your design. Native program execution is the only way for high speed simulation.

GHDL offers three machine code generation backends: one based on GCC, one using the LLVM compiler suite and a GHDL specific one called mcode. These are available in the ghdl-gcc, ghdl-llvm and ghdl-mcode packages respectively. Both the GCC and LLVM backends create highly optimized code for excellent simulation performance while simulations compiled with the GCC backend also allow coverage testing using gcov. The mcode backend creates less performant code but makes up for it with much faster compilation. It is therefore preferable for smaller projects without large or long running simulations.

Multiple backends can be installed at the same time and selected by either invoking the desired GHDL directly (as ghdl-gcc, ghdl-llvm or ghdl-mcode) or by providing a GHDL_BACKEND environment variable (containing gcc, llvm or mcode) while invoking ghdl.

This package is a dependency package that will make sure at least one backend is installed.

gtkwave is a viewer for VCD (Value Change Dump) files which are usually created by digital circuit simulators. (These files have no connection to video CDs!)

IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

MyHDL turns Python into a hardware description and verification language, providing hardware engineers with the power of the Python ecosystem.

Python can then be used as an event-driven simulator using Python decorators actively to specify what corresponds to 'processes' in Verilog / VHDL and thereby achieve concurrency.

This package installs the library for Python 3.

Qrouter is a tool to generate metal layers and vias to physically connect together a netlist in a VLSI fabrication technology. It is a maze router, otherwise known as an "over-the-cell" router or "sea-of-gates" router. That is, unlike a channel router, it begins with a description of placed standard cells, usually packed together at minimum spacing, and places metal routes over the standard cells.

Qrouter uses the open standard LEF and DEF formats as file input and output. It takes the cell definitions from a LEF file, and analyzes the geometry for each cell to determine contact points and route obstructions. It then reads the cell placement, pin placement, and netlist from a DEF file, performs the detailed route, and writes an annotated DEF file as output.

Simulide is a real time electronic circuit simulator intended for hobbist and student experimentation with simple general purpose electronic circuits and PIC, AVR and Arduino microcontroller simulations.

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.