Debian Electronics ASIC development packages

Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including custom IC layout (ASICs), schematic drawing, hardware description language specifications, and electro-mechanical hybrid layout.

gtkwave is a viewer for VCD (Value Change Dump) files which are usually created by digital circuit simulators. (These files have no connection to video CDs!)

Gwave is a tool for viewing analog data, such as the output of Spice simulations.

Gwave can read "raw" files from spice2G6, spice3F5 or ngspice, and a tabular ASCII format suitable for use with GnuCAP or homegrown tools. It can also read several binary and ascii files written by commercial spice-type simulators such as hspice, tspice, and nanosim.

It supports multiple "panels" (graticules) with multiple variables displayed in each. Two vertical-bar cursors are available for time-difference measurements. Multiple files can be loaded, for comparing results of several simulations.

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is very good viewer for GDSII and other layout files used in the semiconductor industry.

It is similar to 'magic', but has a much more modern GUI and is more robust handling all kinds of GDSII files created by various other tools. Its focus is more on viewing than on editing, but it also has limited, but expanding, support for DRC and extraction for LVS.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit.

Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time.

Note that the executable name in Debian is 'netgen-lvs'. For details, see /usr/share/doc/netgen-lvs/README.Debian

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

Qrouter is a tool to generate metal layers and vias to physically connect together a netlist in a VLSI fabrication technology. It is a maze router, otherwise known as an "over-the-cell" router or "sea-of-gates" router. That is, unlike a channel router, it begins with a description of placed standard cells, usually packed together at minimum spacing, and places metal routes over the standard cells.

Qrouter uses the open standard LEF and DEF formats as file input and output. It takes the cell definitions from a LEF file, and analyzes the geometry for each cell to determine contact points and route obstructions. It then reads the cell placement, pin placement, and netlist from a DEF file, performs the detailed route, and writes an annotated DEF file as output.

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance provides CAD tools covering most of all the digital design flow:

• VHDL Compilation and Simulation
• Model checking and formal proof
• RTL and Logic synthesis
• Data-Path compilation
• Macro-cells generation
• Place and route
• Layout edition
• Netlist extraction and verification
• Design rules checking

The command line tool can be used for reporting statistics on GDSII geometries and export them to other file formats, notably including the GMSH geometry format.

It is the "example application" for libGDSII which is a C++ library for working with GDSII binary data files.

This package also contains example GDSII files.

This is a C++ library for working with GDSII binary data files, intended primarily for use with the computational electromagnetism codes scuff-em and meep but sufficiently general-purpose to allow other uses as well.

This package contains the development files for the library.

Gdspy is a Python module for creating/importing/merging GDSII stream files. It includes key libraries for creating complex CAD layouts.

Features:

• Boolean operations on polygons (AND, OR, NOT, XOR) based on clipping algorithm
• Polygon offset (inward and outward rescaling of polygons)
• Efficient point-in-polygon solutions for large array sets

This package installs the library for Python 3.

Coriolis is a set of tools for VLSI backend flow.

It's main features are:

• An analytic placer Etesian (based on Coloquinte).
• A router Katana for digital designs. An extension toward mixed design is currently under development.
• Python fast prototyping capabilities and layout procedural description.