Debian Electronics Simulation packages

GHDL is a compiler and simulator for VHDL, a Hardware Description Language. GHDL is not an interpreter: it allows you to analyse and elaborate sources to generate machine code from your design. Native program execution is the only way for high speed simulation.

GHDL offers three machine code generation backends: one based on GCC, one using the LLVM compiler suite and a GHDL specific one called mcode. These are available in the ghdl-gcc, ghdl-llvm and ghdl-mcode packages respectively. Both the GCC and LLVM backends create highly optimized code for excellent simulation performance while simulations compiled with the GCC backend also allow coverage testing using gcov. The mcode backend creates less performant code but makes up for it with much faster compilation. It is therefore preferable for smaller projects without large or long running simulations.

Multiple backends can be installed at the same time and selected by either invoking the desired GHDL directly (as ghdl-gcc, ghdl-llvm or ghdl-mcode) or by providing a GHDL_BACKEND environment variable (containing gcc, llvm or mcode) while invoking ghdl.

This package is a dependency package that will make sure at least one backend is installed.

Gnucap is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, Fourier analysis, and ac analysis linearized at an operating point. It is fully interactive and command driven. It can also be run in batch mode or as a server.

This package contains a main executable and gnucap-modelgen.

gtkwave is a viewer for VCD (Value Change Dump) files which are usually created by digital circuit simulators. (These files have no connection to video CDs!)

Gwave is a tool for viewing analog data, such as the output of Spice simulations.

Gwave can read "raw" files from spice2G6, spice3F5 or ngspice, and a tabular ASCII format suitable for use with GnuCAP or homegrown tools. It can also read several binary and ascii files written by commercial spice-type simulators such as hspice, tspice, and nanosim.

It supports multiple "panels" (graticules) with multiple variables displayed in each. Two vertical-bar cursors are available for time-difference measurements. Multiple files can be loaded, for comparing results of several simulations.

IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

NGSpice is a mixed-level/mixed-signal circuit simulator. Its code is based on three open source software packages: Spice3f5, Cider1b1 and Xspice. It supports compiled Verilog-A models through the built-in OSDI interface.

NGSpice is part of gEDA project, a full GPL'd suite of Electronic Design Automation tools.

Oregano je aplikace GNOME určená pro schématické snímání a tisk elektronických obvodů. Program umí simulovat obvody za pomoci Gnucap, ng-spice nebo Berkeley spice.

Simulide is a real time electronic circuit simulator intended for hobbist and student experimentation with simple general purpose electronic circuits and PIC, AVR and Arduino microcontroller simulations.

TkGate is a digital circuit editor and simulator with a Tcl/Tk based interface. TkGate includes a large number of built-in devices including basic gates, memories, ttys and modules for hierarchical design. The simulator can be controlled either interactively or through a simulation script. Memory contents can be loaded from files, and a microcode/macrocode compiler (gmac) is included to create tkgate memory files from a high-level description. The simulator supports continuous simulation, single step simulation (by clock or epoch) and breakpoints. Save files are in a Verilog-like format.

TkGate also includes a number of tutorial and example circuits which can be loaded through the "Help" menu. The examples range from a simple gate-level 3-bit adder to a 16-bit CPU programmed to play the "Animals" game.

TkGate has a multi-language interface with support for English, Japanese, French and Spanish.

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

This package contains Python bindings for the GNU Circuit Analysis Package.

Gnucap is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, Fourier analysis, and ac analysis linearized at an operating point. It is fully interactive and command driven. It can also be run in batch mode or as a server.