Debian Electronics Simulation packages

GHDL is a compiler and simulator for VHDL, a Hardware Description Language. GHDL is not an interpreter: it allows you to analyse and elaborate sources to generate machine code from your design. Native program execution is the only way for high speed simulation.

GHDL offers three machine code generation backends: one based on GCC, one using the LLVM compiler suite and a GHDL specific one called mcode. These are available in the ghdl-gcc, ghdl-llvm and ghdl-mcode packages respectively. Both the GCC and LLVM backends create highly optimized code for excellent simulation performance while simulations compiled with the GCC backend also allow coverage testing using gcov. The mcode backend creates less performant code but makes up for it with much faster compilation. It is therefore preferable for smaller projects without large or long running simulations.

Multiple backends can be installed at the same time and selected by either invoking the desired GHDL directly (as ghdl-gcc, ghdl-llvm or ghdl-mcode) or by providing a GHDL_BACKEND environment variable (containing gcc, llvm or mcode) while invoking ghdl.

This package is a dependency package that will make sure at least one backend is installed.

Gnucap is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, Fourier analysis, and ac analysis linearized at an operating point. It is fully interactive and command driven. It can also be run in batch mode or as a server.

This package contains a main executable and gnucap-modelgen.

gtkwave is a viewer for VCD (Value Change Dump) files which are usually created by digital circuit simulators. (These files have no connection to video CDs!)

Gwave는 Spice의 출력같은 아날로그 데이타를 보기 위한 도구입니다.

Gwave는 spice2G6, spice3F5 또는 ngspice에서 "raw" 파일을 읽을 수 있으며, 그 리고 표로 된 ASCII 형식은 GnuCAP 또는 자체 개발한 도구와 작업하기에 적합합 니다. Gwave는 또한 HSPICE, tspice 그리고 nanosim 같은 상용 spice-type 시뮬 레이터에 의해 작성된 여러 파일과 ascii 파일을 읽을 수 있습니다.

Gwave는 각각 표시되는 여러 변수를 갖는 다중 "패널" (격자선)을 지원합니다. 두 개의 수직 막대 커서는 시간 차이 측정에 사용할 수 있습니다. 여러 파일은 여러 시뮬레이션 결과 비교를 위해 로드될 수 있습니다.

IRSIM은 디지탈 회로를 시뮬레이션하기 위하나 도구입니다. "switch-level"에 시뮬레이터입니다; 트랜지스터를 이상적인 스위치로 취급합니다. 추출된 커패시턴스 및 집중 저항 값은 RC 시간 상수를 사용하여 이벤트의 상대적 타이밍을 예측하여 스위치를 이상적인 것 보다 조금 더 현실적으로 만드는데 사용됩니다.

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

NGSpice is a mixed-level/mixed-signal circuit simulator. Its code is based on three open source software packages: Spice3f5, Cider1b1 and Xspice. It supports compiled Verilog-A models through the built-in OSDI interface.

NGSpice is part of gEDA project, a full GPL'd suite of Electronic Design Automation tools.

Oregano는 도식 캡쳐 및 전자 회로 프린팅을 위한 그놈 어플리케이션입니다. Gnucap, ng-spice 또는 Berkeley spice를 사용해서 회로를 시뮬레이트할 수 있습 니다.

Simulide is a real time electronic circuit simulator intended for hobbist and student experimentation with simple general purpose electronic circuits and PIC, AVR and Arduino microcontroller simulations.

TkGate is a digital circuit editor and simulator with a Tcl/Tk based interface. TkGate includes a large number of built-in devices including basic gates, memories, ttys and modules for hierarchical design. The simulator can be controlled either interactively or through a simulation script. Memory contents can be loaded from files, and a microcode/macrocode compiler (gmac) is included to create tkgate memory files from a high-level description. The simulator supports continuous simulation, single step simulation (by clock or epoch) and breakpoints. Save files are in a Verilog-like format.

TkGate also includes a number of tutorial and example circuits which can be loaded through the "Help" menu. The examples range from a simple gate-level 3-bit adder to a 16-bit CPU programmed to play the "Animals" game.

TkGate has a multi-language interface with support for English, Japanese, French and Spanish.

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

This is a free VHDL simulator with these features:

• Has a graphical waveform viewer.
• Has a source level debugger.
• Is VHDL-93 compliant.

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

This package contains Python bindings for the GNU Circuit Analysis Package.

Gnucap is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, Fourier analysis, and ac analysis linearized at an operating point. It is fully interactive and command driven. It can also be run in batch mode or as a server.

Easyspice is a graphical frontend for the electrical circuit simulator Spice. It is by default connected to the geda package and ngspice but can be used as a frontend for other spice simulators programs as well.