Debian Electronics ASIC development packages

Electric은 사용자 지정 IC 레이아웃(ASICs), 개요 그림, 하드웨어 기술 언어 설계 명세서, 그리고 전기 기계 혼합 레이아웃등을 포함하는, 회로 설계의 많은 폼을 처리할 수 있는 세련된 전자 CAD 시스템입니다.

gtkwave is a viewer for VCD (Value Change Dump) files which are usually created by digital circuit simulators. (These files have no connection to video CDs!)

Gwave는 Spice의 출력같은 아날로그 데이타를 보기 위한 도구입니다.

Gwave는 spice2G6, spice3F5 또는 ngspice에서 "raw" 파일을 읽을 수 있으며, 그 리고 표로 된 ASCII 형식은 GnuCAP 또는 자체 개발한 도구와 작업하기에 적합합 니다. Gwave는 또한 HSPICE, tspice 그리고 nanosim 같은 상용 spice-type 시뮬 레이터에 의해 작성된 여러 파일과 ascii 파일을 읽을 수 있습니다.

Gwave는 각각 표시되는 여러 변수를 갖는 다중 "패널" (격자선)을 지원합니다. 두 개의 수직 막대 커서는 시간 차이 측정에 사용할 수 있습니다. 여러 파일은 여러 시뮬레이션 결과 비교를 위해 로드될 수 있습니다.

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

This is very good viewer for GDSII and other layout files used in the semiconductor industry.

It is similar to 'magic', but has a much more modern GUI and is more robust handling all kinds of GDSII files created by various other tools. Its focus is more on viewing than on editing, but it also has limited, but expanding, support for DRC and extraction for LVS.

Magic은 1980년대 버클리에서 John Ousterhout가 개발한 유서깊은 VLSI 레이아웃 도구로, 현재는 주로 스크립트 인터프리터 언어 Tcl 개발로 유명합니다. 대체적으로 진보적인 버클리 오픈소스 라이센스 덕에 Magic은 대학과 소규모 회사에서 여전히 인기를 끌고 있습니다. 오픈소스 라이센스를 통해 프로그램에 관심이 있는 VLSI 엔지니어가 자신의 스마트한 아이디어를 구현하고 magic이 제조 기술을 따라 잡을 수 있도록 합니다. 그러나 magic에 적합한 가장 인기있는 분야는 잘 고안된 코어 알고리즘입니다. Magic은 궁극적으로 제품 설계 흐름을 위해 사용 도구를 사용하는 사람들에게도 회로 레이아웃에 사용하기 가장 쉬운 도구로 널리 알려져 있습니다.

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit.

Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time.

Note that the executable name in Debian is 'netgen-lvs'. For details, see /usr/share/doc/netgen-lvs/README.Debian

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

Qrouter is a tool to generate metal layers and vias to physically connect together a netlist in a VLSI fabrication technology. It is a maze router, otherwise known as an "over-the-cell" router or "sea-of-gates" router. That is, unlike a channel router, it begins with a description of placed standard cells, usually packed together at minimum spacing, and places metal routes over the standard cells.

Qrouter uses the open standard LEF and DEF formats as file input and output. It takes the cell definitions from a LEF file, and analyzes the geometry for each cell to determine contact points and route obstructions. It then reads the cell placement, pin placement, and netlist from a DEF file, performs the detailed route, and writes an annotated DEF file as output.

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance provides CAD tools covering most of all the digital design flow:

• VHDL Compilation and Simulation
• Model checking and formal proof
• RTL and Logic synthesis
• Data-Path compilation
• Macro-cells generation
• Place and route
• Layout edition
• Netlist extraction and verification
• Design rules checking

The command line tool can be used for reporting statistics on GDSII geometries and export them to other file formats, notably including the GMSH geometry format.

It is the "example application" for libGDSII which is a C++ library for working with GDSII binary data files.

This package also contains example GDSII files.

This is a C++ library for working with GDSII binary data files, intended primarily for use with the computational electromagnetism codes scuff-em and meep but sufficiently general-purpose to allow other uses as well.

This package contains the development files for the library.

Gdspy is a Python module for creating/importing/merging GDSII stream files. It includes key libraries for creating complex CAD layouts.

Features:

• Boolean operations on polygons (AND, OR, NOT, XOR) based on clipping algorithm
• Polygon offset (inward and outward rescaling of polygons)
• Efficient point-in-polygon solutions for large array sets

This package installs the library for Python 3.

Coriolis is a set of tools for VLSI backend flow.

It's main features are:

• An analytic placer Etesian (based on Coloquinte).
• A router Katana for digital designs. An extension toward mixed design is currently under development.
• Python fast prototyping capabilities and layout procedural description.